Low Power and Reliable Design for Emerging Tecnologies

Yuanqing Cheng - Beihang University
Data e ora
martedì 30 ottobre 2018 alle ore 16.30 - Sala verde
Referente esterno
Data pubblicazione
6 settembre 2018


As the technology node continuously scales down, Moore’s law may not be sustainable as before for conventional CMOS technology. To deal with this challenge, several emerging memory technologies have been proposed as promising cadidates of SRAM. Among them, spintronic and carbon nanotube devices have unique desirable merits, such as non-volatitliy, fast access speed, high endurance, ultra low leakage power and compatiblity with CMOS process. Therefore, they are promising cadidates for next generation of logic and memory design. On the other hand, since the fabrication processes of STT-MRAM and carbon nanotube devices are not mature yet, it is imperative to enhance the reliability and the energy efficiency from both circuit level and architecture level perspectives to guarantee the commercial success of these emerging technologies. In this talk, I will introduce my group’s several relevant work on low power and reliability design of STT-MRAM and carbon nanotube based memory. During this talk, I will also briefly introduce Beihang University and expect to establish the collaborations with University of Verona.

Contact person: Franco Fummi

© 2002 - 2021  Universit√† degli studi di Verona
Via dell'Artigliere 8, 37129 Verona  |  P. I.V.A. 01541040232  |  C. FISCALE 93009870234