An Energy-Efficient Patchable Accelerator For Post-Silicon Engineering Change and Debugging

Relatore
Prof. Masahiro Fujita - University of Tokyo - VLSI Design and Education Center (VDEC)
Data e ora
lunedì 18 luglio 2011 alle ore 10.15 - 10:15 rinfresco; 10:30 inizio seminario
Luogo
Ca' Vignal - Piramide, Piano 0, Sala Verde
Referente
Tiziano Villa
Referente esterno
Data pubblicazione
30 giugno 2011
Dipartimento
Informatica  

Riassunto

With the shorter time-to-market and the rising cost in SoC development, the demand for post-silicon programmability has been increasing. Recently, programmable accelerators have attracted more attention as an enabling solution for post-silicon engineering change. However, programmable accelerators suffers from 5∼10X less energy efficiency than fixed-function accelerators mainly due to their extensive use of memories. This paper proposes a highly energy-efficient accelerator which enables post-silicon engineering change by a control patching mechanism. Then, we propose a patch compilation method from a given pair of an original design and a modified design. Experimental results demonstrate that the proposed accelerators offer high energy efficiency competitive to fixed-function accelerators and can achieve about 5X higher efficiency than the existing programmable accelerators.





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