Technology Mapping with Choices, Priority Cuts, and Placement-Aware Heuristics

Supervisor
Alan Mishchenko - Dept. of EECS, University of California, Berkeley, USA
Date and time
Tuesday, May 18, 2010 at 4:45 PM - Ore 16.45 caffe' e pasticcini, ore 17 inizio seminario
Place
Ca' Vignal - Piramide, Floor 0, Hall Verde
Programme Director
Tiziano Villa
External reference
Publication date
May 6, 2010
Department
Computer Science  

Summary

 This talk introduces the topic of technology mapping and presents an
algorithm for mapping logic networks into K-input lookup-tables (K-LUTs).
The algorithm avoids the hurdles of computing all K input cuts while
preserving the quality of the results, in terms of area and depth. The
memory and runtime of the proposed algorithm are linear in circuit size
and quite affordable even for large industrial designs. An extension of
the algorithm allows for sequential mapping, which searches the combined
space of all mappings and retimings. This leads to an average 20%
improvement in depth with a marginal area penalty, compared to
combinational mapping followed by retiming.






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